Analog-to-Digital Converter circuits (ADCs) are often implemented with Sigma-Delta topologies when high accuracy is required.
An example of application is in the audio field, where Sigma-Delta ADCs are the most commonly used.
As known, this topology of converters transforms an analog input signal to a digital stream of words with a low number of bits and a spectrally-shaped quantization noise.
The first Sigma-Delta converters had a single bit output (2 levels), then they evolved to multi-level outputs thanks to the usage of new design techniques.
The multi-level solution has the advantage of reducing the quantization noise at the cost of an increased complexity of the ADCs.
For this reason the output bits of these converters are mainly in the range of one (2 levels) to 5 (32 levels) and more rarely they go beyond these numbers.
FIG. 1 shows a multi-level second-order sigma-delta converter 100 of the prior art in which the shown quantizer 101 is L-levels.
The converter 100 of FIG. 1 is arranged to convert an input analog signal X into a stream of digital words Y.
The converter 100 includes a direct path d1 having a first analog integrator 102 and a second analog integrator 103 connected in series one another upstream the quantizer 101. The converter 100 further comprises a feedback path f1 arranged to subtract an analog signal corresponding the digital output signal Y from the input of the first analog converter 102 and the second analog converter 103, respectively.
As known, the quantizer must not introduce substantial delay in the direct path because the delay can cause instability, so the preferred solution to implement the quantizer is to do a flash-converter with a number of comparators equal to the output levels minus one (in this example L−1 comparators).
Other methods are possible to implement this block, but in any case low delay and L-levels accuracy is required.
In most cases the complexity of the quantizer is the limiting factor for the increase of the number of levels.
An example of multi level sigma-delta is described in the publication “Third-Order Sigma-Delta Modulator with 61-dB SNR and 6-MHz Bandwidth Consuming 6 mW”, Bonizzoni et al., University of Pavia, 2008, IEEE.
US 2003/081687 A1 describes a three order sigma-delta modulator having a feedback and a feedforward configuration.
US 2010/164769 A1 discloses a sigma-delta modulator architecture capable of automatically improving dynamic range.
US 2007/210947 A1 relates to an arrangement of feedback resisters for the sigma-delata analog-to-digital converter (ADC).